factory programmable quad pll clock generator with vcxo cy22388/89/91 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07734 rev. *b revised october 10, 2006 features ? fully integrated phase-locked loops (plls) ? qfn package: ? 40% smaller than 20-pin tssop ? 22% smaller than 16-pin tssop ? selectable output frequency ? programmable output frequencies ? o u t p u t f r e q u e n c y r a n g e o f 5 C 1 6 6 m h z ? input frequency range ? c r y s t a l : 1 0 C 3 0 m h z ? e x t e r n a l r e f e r e n c e : 1 C 1 0 0 m h z ? analog vcxo ? 16-/20-pin tssop and 32-pin qfn packages ? 3.3v operation with 2.5v output buffer option benefits ? meets most digital set top box, dvd recorder, and dtv application requirements ? multiple high-performance plls allow synthesis of unrelated frequencies ? integration eliminates the need for external loop filter components ? meets critical timing requirements in complex system designs ? enables application compatibility ? c o m p l e t e v c x o s o l u t i o n w i t h 1 2 0 p p m ( t y p i c a l p u l l r a n g e ) c y 2 23 88 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 x in fs 0 fs 1 v in v d d v s s c lk a c lk b c lk c c lk d c lk e v s s v d d f s 2 v d d x o u t 16 - p in ts s o p block diagram pin configurations c y 22389 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 x in fs 0 fs 1 clkh vdd vss clkd clkb clk g vss vd d vin fs 2 o e / p d vd d xo ut clka clk f clkc clk e 9 12 10 11 20 - p in tsso p 1 2 3 4 5 6 8 7 2 4 2 3 2 2 2 1 2 0 1 9 1 7 1 8 1 6 1 5 1 4 1 3 1 2 1 1 9 1 0 3 2 3 1 3 0 2 9 2 8 2 7 2 5 2 6 c y 2 2 3 9 1 v in v d d v d d v s s v s s v s s v s s c l k h c l k d c l k b c l k a n c n c c l k c c l k e v d d c l k f c l k g v s s v s s v d d v d d f s 2 o e / p d # v d d v d d x o u t n c n c x i n f s 0 f s 1 3 2 - p in q f n vc x o p ll1 p ll2 p ll3 p ll4 c lk a c lk b c lk h c lk c c lk d c lk e c lk f c lk g d ivider & m ultiplexer x in x o u t s elect logic fs 0/1/2 o e v in vc x o p ll1 p ll2 p ll3 p ll4 c lk a c lk b c lk h c lk c c lk d c lk e c lk f c lk g d ivider & m ultiplexer x in x o u t s elect logic fs 0/1/2 o e v in [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 2 of 10 general description the cy22388 family of devices has an analog vcxo (voltage controlled crystal oscillator), 4 plls, up to 8 clock outputs and frequency selection capabilities. the frequency selects do not modify any pll frequency. instead they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. this is illustrated in the following frequency selection tables and functional block diagram. there is one programmable oe/pdwn. the oe/pdwn pin can be programmed as either an output enable pin or a power-down pin. the oe function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. full-chip power down will disable all outputs as well as the plls and most of the active circuitry when low. factory-programmable cy22388/89/91 factory programming is available for high- or low-volume manufacturing by cypress. all requests must be submitted to the local cypress field application engineer (fae) or sales representative. once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. this part number will be used for additional sample requests and production orders. plls the advantage of having four plls is that a single device can generate up to four independent frequencies from a single crystal. generally a design may require up to four oscillators to accomplish what could be done with a single cy22388. each pll is independent and can be configured to generate a vco (voltage controlled oscillator) frequency between 62.5 mhz and 250 mhz. each pll can then in turn be divided down with post dividers to generate the clock output frequency o f t h e u s e r s c h o i c e . t h e o u t p u t d i v i d e r a l l o w s e a c h c l o c k output to be divided by 1,2,3,4,5,6,8,9,10,12,15. the pll maximum is reduced to 166 mhz in divide by 1 mode due to output buffer limitations. outputs that allow frequency switching perform the transition free of glitches. a glitch is defined as a high or low time shorter than half the smaller of the two periods being switched between. extended low time (even many cycles in duration) is acceptable. selected clock outputs are capable of being powered off a separate 2.5v supply. this will allow for driving lower voltage swing inputs. the cy22388/89/91 device still requires 3.3v to power the oscillator and all other internal pll circuitry. for the 2.5v output option please refer to the cy22388 application note. selected clocks and pinout diagrams will be explained in this application note. clock d can obtain its output from either the reference source or pll1/n1 with n1 being defined as the output divider for pll1. clock h is defined as a copy of clock d. clock d is only available from pll1/n1 on the 16-pin package. for cy22388, clkb and clkc have related frequencies. for cy22389 and cy22391, clkd and clkf have related frequencies, clka and clkb have related frequencies, and pin description pin name pin number pin description 16-pin tssop 20-pin tssop 32-pin qfn xin 1 1 30 crystal input or reference clock input xout 16 20 27 crystal output (no connect if external clock is used) clka 7 9 11 clock output clkb 8 8 10 clock output clkc 9 10 14 clock output clkd 10 7 9 clock output clke 11 11 15 clock output clkf n/a 12 17 clock output clkg n/a 13 18 clock output clkh n/a 4 8 clock output fs0 2 2 31 frequency select 0 fs1 3 3 32 frequency select 1 fs2 14 17 23 frequency select 2 oe/pd n/a 18 24 output enable control/power down vin 4 16 1 analog control input for vcxo vdd 5,13,15 5,15,19 2,3,16,21,22,25,26 voltage supply vss 6,12 6,14 4,5,6,7,19,20 ground nc n/a n/a 12,13,28,29 no connect. [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 3 of 10 clkc and clke have related frequencies. related frequencies come from the same pll but can have different divider values. in order to minimize ppm (parts per million) error on the clock outputs, a user should choose a crystal reference frequency that is a common multiple of the desired pll frequencies. while this would be the ideal situation, this is not always the case and the plls have high-resolution counters internally to help minimize frequency deviation from the desired frequency. pll vco frequencies are generated by the following equation: f vco = f ref * (p / q) where f ref is the reference input frequency, p is the pll feedback divider and q is the reference input divider. a pll is a feedback system where the vco frequency divided by p and reference frequency divided by q are constantly being compared and the vco frequency is adjusted to achieve a locked state. figure 1 is a simplified drawing of a pll. figure 1. frequency select pin operation f r e f / q v c o a n d o t h e r c o m p o n e n t s / p f v c o table 1. cy22388 16-pin tssop output signal frequency selection lines clock a s2s1s0 clock b s1s0 clock c & clock d s0 clock e fixed table 2. cy22389 20-pin tssop output signal frequency selection lines clock a s2s1s0 clock b & clock c s1s0 clock d, clock e, & clock f s0 clock g fixed clock h copy of clock d table 3. cy22391 32-pin qfn output signal frequency selection lines clock a s2s1s0 clock b & clock c s1s0 clock d, clock e, & clock f s0 clock g fixed clock h copy of clock d [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 4 of 10 analog vcxo there are three programmable reference operating modes for the cy22388/89/91 family of devices. the first mode utilizes an external pullable crystal and incorporates an internal analog vcxo. the second mode configures the internal crystal oscillator to accept an external driven reference source from 1 to 100 mhz. the input capacitance on the xin pin when driven in this mode is 15 pf. the third mode disables the vcxo input control and sets the internal oscillator to a fixed frequency operation. the load capacitance seen by the external crystal when connected to pins xin and xout is equal to 12 pf. one of the key components to the cy22388/89/91 family of d e v i c e s i s t h e a n a l o g v c x o . t h e v c x o i s u s e d t o p u l l t h e reference crystal higher or lower in order to lock the system frequency to an external source. this is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. the vcxo is completely analog, so there is infinite resolution on the vcxo pull curve. the analog to digital converter steps that are normally associated with a digital vcxo input is not present in this device. a special pullable crystal must be used to in order to have adequate vcxo pull range. pullable crystal specifications are included in this data sheet. please refer to the cy22388/89/91 application note for pullable crystal recommendations outside of the standard industry frequencies given in the pullable crystal specifica- tions. vcxo profile figure 2 shows an example of what a vcxo profile looks like. the analog voltage input is on the x-axis and the ppm range is on the y-axis. an increase in the vcxo input voltage results in a corresponding increase in the output frequency. this has the effect of moving the ppm from a negative to positive offset. figure 2. vcxo profile . -200 -150 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 3 3.5 vcxo input [v] t u n i n g [ p p m ] [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 5 of 10 absolute maximum conditions parameter description condition min. max. unit v dd /av dd /v ddl core supply voltage C 0 . 5 4.6 v v in input voltage relative to v ss C 0 . 5 v dd + 0.5 vdc t s temperature, storage non-functional C 6 5 +125 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 C volts ul-94 flammability rating v-0 @1/8 in. C 10 ppm msl moisture sensitivity level qfn package 3 16- and 20-pin tssop 1 pullable crystal specifications [1, 3] parameter description comments min. typ. max. unit f nom 13.5-mhz and 27-mhz crystal at-cut parallel resonance, fundamental mode see note 3 c lnom nominal load capacitance order crystal at one specific c lnom 0 ppm 11.4 12 12.6 pf r 1 equivalent series resistance (esr) fundamental mode (cl = series) C C 40 ? dl crystal drive level n o m i n a l v d d @ 2 5 c o v e r 1 2 0 p p m pull range C C 300 ? w c 0 [2] crystal shunt capacitance 1.5 3 4.0 pf c 1 [2] crystal motional capacitance 12 14 16.8 ff f 3sephi [3] third overtone separation from 3*f nom mechanical third (high side of 3*f nom ) 240 C C ppm f 3seplo [3] third overtone separation from 3*f nom mechanical third (low side of 3*f nom ) C C C 1 2 0 ppm recommended operating conditions parameter description min. typ. max. unit v dd /av dd /v ddl operating voltage 3.0 3.3 3.6 v t a ambient temperature C 1 0 C 70 c c load maximum load capacitance C C 15 pf t pu power-up time for all v dd s reach minimum specified voltage (power ramps must be monotonic) 0.05 C 500 ms notes 1. device operates to the following specs, which are guaranteed by design. 2. i n c r e a s e d t o l e r a n c e a v a i l a b l e f r o m p u l l r a n g e l e s s t h a n 1 2 0 p p m . 3. refer to cy22388 application note and online software for a list of approved crystal specifications. [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 6 of 10 dc parameters [4] parameter description conditions min. typ. max. unit i oh [5] output high current v oh = v dd C 0 . 5 , v dd = 3.3v 12 C C ma i ol [5] output low current v ol = 0.5, v dd = 3.3v 12 C C ma i ih input high current v ih = v dd , excluding vin, xin C 5 10 a i il input low current v il = 0v, excluding vin, xin C 5 10 a v ih input high voltage fs0/1/2 oe input cmos levels 0.7xa vdd C C v v il input low voltage fs0/1/2 oe input cmos levels C C 0.3xa vdd v v vcxo vin input range 0 C a vdd v c in input capacitance fs0/1/2 and oe pins only C C 7 pf i vdd supply current v dd /av dd /v ddl current C 60 C ma c inxin input capacitance at xin vcxo disabled external reference C 15 C pf c inxtal input capacitance at crystal vcxo disabled fixed freq. oscillator C 12 C pf notes 4. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loa ded outputs. 5. custom drive level and is available upon request ac parameters parameter [4] description conditions min. typ. max. units 1/t1 output frequency pll minmax /divider maximum 4.2 C 166 mhz dc1 output duty cycle (excluding refout ? duty cycle is defined in figure 4 ; t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is ? ? 125 mhz) 45 50 55 % dc2 output duty cycle duty cycle is defined in figure 4 ; t 2 /t 1 , 50% of v dd external reference duty cycle between 40% and 60% measured at v dd /2 (clock output is ? ? 125 mhz) 40 50 60 % dc refout output duty cycle duty cycle is defined in figure 4 ; t 2 /t 1 , 50% of v dd (xin duty cycle = 45/55%) 40 50 60 % er rising edge rate output clock edge rate. measured from 20% to 80% of v dd . c load = 15 pf. see figure 5 . 0.75 1.2 C v/ns ef falling edge rate output clock edge rate. measured from 80% to 20% of v dd . c load = 15pf see figure 5 . 0.75 1.2 C v/ns t 9 clock jitter period jitter C 2 5 0 C ps t 10 pll lock time C 1 5 ms f ? xo vcxo crystal pull range using non- smd-49 crystal specified in c y 2 2 3 8 8 a p p l i c a t i o n n o t e , a n c 0 0 0 2 n o m i n a l c r y s t a l f r e q u e n c y i n p u t a s s u m e d ( 0 p p m ) @ 2 5 c a n d 3 . 3 v 1 1 0 1 2 0 C ppm using smd-49 crystal specified in c y 2 2 3 8 8 a p p l i c a t i o n n o t e , a n c 0 0 0 2 n o m i n a l c r y s t a l f r e q u e n c y i n p u t a s s u m e d ( 0 p p m ) @ 2 5 c a n d 3 . 3 v 1 0 5 1 2 0 C ppm [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 7 of 10 test and measurement set-up figure 3. test and measurement voltage and timing definitions figure 4. duty cycle definition figure 5. er = (0.6 ? ? v dd )/t 3 , ef = (0.6 ? ? v dd )/t 4 figure 6. fs controlled clock output d u t v d d s o utputs c lo a d g n d 0.1 ? f t 2 t 1 clock o utput 0v v dd 50% of v dd t 3 t 4 80% of v dd 20% of v dd clock o utput v dd 0v start at full cycle finish cycle t wait fs [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 8 of 10 package drawing and dimensions figure 7. 16-lead tssop 4.40 mm body z16.173 note 6. the cy22388zxc-xxx, cy22389zxc-xxx, and CY22391LFXC-XXX are factory programmed configurations. for more details, contact your lo cal cypress fae or cypress sales representative. ordering information part number [6] type production flow lead-free cy22388zxc-xxx 16-pin tssop c o m m e r c i a l , 0 c t o + 7 0 c cy22389zxc-xxx 20-pin tssop c o m m e r c i a l , 0 c t o + 7 0 c CY22391LFXC-XXX 32-pin qfn c o m m e r c i a l , 0 c t o + 7 0 c 51-85091-*a [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 9 of 10 ? c y p r e s s s e m i c o n d u c t o r c o r p o r a t i o n , 2 0 0 6 . t h e i n f o r m a t i o n c o n t a i n e d h e r e i n i s s u b j e c t t o c h a n g e w i t h o u t n o t i c e . c y p r e s s s e m i c o n ductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or oth er rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agre ement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to res ult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnif ies cypress against all charges. figure 8. 20-lead thin shrunk small outline package (4.40-mm body) z20 figure 9. 32-lead qfn (5 x 5 mm) lf32a all product and company names mentioned in this document are trademarks of their respective holder. 51-85118-*a 51-85188-*a [+] feedback [+] feedback
cy22388/89/91 document #: 38-07734 rev. *b page 10 of 10 document history page document title: cy22388/89/91 factory programmable quad pll clock generator with vcxo document number: 38-07734 rev. ecn no. issue date orig. of change description of change ** 320458 see ecn rgl new data sheet *a 389649 see ecn rgl changed r1 value to max. 40 ? changed dl comments and max. value to 300 ? w changed f ? xo m i n . v a l u e t o 1 1 0 p p m a n d t y p . v a l u e t o 1 2 0 p p m *b 523597 see ecn rgl specified a non-smd-49 and smd-49 crystal specs in the vcxo pull range parameter [+] feedback [+] feedback
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